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CS4373 Low-power, High-performance Test DAC
Features
* Digital Input, Differential Analog Output * Selectable Differential Outputs (OUT, BUF) * Selectable Output Attenuation
- 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64
Description
The CS4373 is a differential output digital-toanalog converter intended for high-resolution, low-frequency measurement systems. It is designed to work with the CS5376A and CS5378 digital filters, the CS3301 and CS3302 high-precision amplifiers, and the CS5371 or CS5372 high-performance modulators. The CS4373 includes a set of multiplexed outputs which provide a precision output (OUT) for testing the electronics channel and a buffered output (BUF) for in-circuit sensor tests. It is driven by a bitstream and the maximum analog output is differential 5 volts peak-to-peak. Distortion performance of the DAC is typically -118 dB THD from the precision output, and -100 dB THD from the buffered output. Noise performance is 114 dB SNR over a 430 Hz bandwidth. The CS4373 has very low power consumption. In normal mode (LPWR=0; MCLK=2.048 MHz), power consumption is 40 mW; while in Low Power mode (LPWR=1; MCLK=1.024 MHz), power consumption is 25 mW.
ORDERING INFORMATION See page 19.
* User-programmable Test Modes
- Differential - Common mode
* Output Voltage: 5 VP-P Differential * Outstanding Noise Performance
- 114 dB SNR @ 430 Hz bandwidth
* Low Total Harmonic Distortion
- OUT: -118 dB THD typical, -112 dB THD max - BUF: -100 dB THD typical, -95 dB THD max
* Low Power Consumption
Normal mode: 7.8 mA Low power mode: 5.0 mA Power down: 400 A Sleep mode: 2 A
* Power Supply Options
- VA+ = +5 V; VA- = 0 V; VD = +3.3 V to +5 V - VA+ = +2.5 V; VA- = -2.5 V; VD = +3.3 V
VA+
MODE(0, 1, 2)
ATT(0, 1, 2)
VD
TDATA
Attenuator
OUT+ OUTBUF+ BUFCAP+ CAP-
24-bit DAC
LPWR
MCLK SYNC
Clock Generator
VA-
VREF+
VREF-
DGND
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved)
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TABLE OF CONTENTS
1. 2. 3. 4. CHARACTERISTICS & SPECIFICATIONS ............................................................................. 4 TERMINOLOGY ........................................................................................................................ 9 GENERAL DESCRIPTION ..................................................................................................... 10 ANALOG OUTPUTS ............................................................................................................... 10 4.1 CAP+ / CAP- .................................................................................................................... 10 4.2 OUT+ / OUT- ................................................................................................................... 10 4.3 BUF+ / BUF- .................................................................................................................... 10 5. DIGITAL FILTER INTERFACE ............................................................................................... 10 5.1 Signal Bitstream Input - TDATA ....................................................................................... 10 5.2 Master Clock - MCLK ....................................................................................................... 10 5.3 Clock Sync Input - SYNC ................................................................................................. 11 6. VOLTAGE REFERENCE ........................................................................................................ 11 6.1 Voltage Reference Inputs ................................................................................................ 11 6.2 Voltage Reference Configurations ................................................................................... 11 6.3 VREF Input Impedance .................................................................................................... 11 6.4 Gain Accuracy .................................................................................................................. 12 6.5 Gain Drift .......................................................................................................................... 12 7. TEST MODES ......................................................................................................................... 13 7.1 Test Mode 0: Reserved .................................................................................................... 13 7.2 Test Mode 1: Sensor Test Mode ...................................................................................... 13 7.3 Test Mode 2: Electronics Test Mode ............................................................................... 14 7.4 Test Mode 3: Sensor Test Mode ...................................................................................... 14 7.5 Test Mode 4: Common Mode .......................................................................................... 14 7.6 Test Mode 5: High Voltage/High Current Mode ............................................................... 14 7.7 Test Mode 6: Reserved .................................................................................................... 14 7.8 Test Mode 7: Sleep Mode ................................................................................................ 14 8. ATTENUATION SETTINGS .................................................................................................... 15 9. POWER MODES ..................................................................................................................... 15 9.1 Normal Power Mode ........................................................................................................ 15 9.2 Low Power Mode ............................................................................................................. 15 9.3 Sleep Mode ...................................................................................................................... 15 9.4 Power Down ..................................................................................................................... 15 10. POWER SUPPLY ................................................................................................................ 15 10.1 Power Supply Bypassing .............................................................................................. 15 10.2 SCR Latch-up Considerations ...................................................................................... 15 10.3 DC-DC Converter Considerations ................................................................................. 16 10.4 Power Supply Rejection ................................................................................................ 16 11. PIN DESCRIPTION ............................................................................................................... 17 12. ORDERING INFORMATION ................................................................................................ 19 13. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .......................... 19 14. REVISION HISTORY ........................................................................................................... 19 15. PACKAGE DIMENSIONS ..................................................................................................... 20
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LIST OF FIGURES
Figure 2. Timing .............................................................................................................................. 7 Figure 1. Rise and Fall Times ......................................................................................................... 7 Figure 4. CS4373 System Connections .......................................................................................... 8 Figure 5. 2.5 Voltage Reference Circuit ........................................................................................ 11 Figure 6. Test Mode 1 ................................................................................................................... 13 Figure 7. Test Mode 4 ................................................................................................................... 13 Figure 8. Test Mode 5 ................................................................................................................... 14
LIST OF TABLES
Table 1. Test Modes ..................................................................................................................... 13 Table 2. Attenuator Selection........................................................................................................ 15 Table 3. Attenuator Selection........................................................................................................ 18 Table 4. Mode Selection ............................................................................................................... 18
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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1. CHARACTERISTICS & SPECIFICATIONS
* * * * * Min / Max characteristics and specifications are guaranteed over all Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25C. DGND = 0 V. All voltages with respect to 0 V. Devices are connected as shown in Figure 4 on page 8 unless otherwise noted. Tests performed using the TBS bitstream at TBSGAIN = 0x4B8F2, unless otherwise noted.
RECOMMENDED OPERATING CONDITIONS
Parameter Positive Digital Power Supply Positive Analog Power Supply Negative Analog Power Supply Voltage Reference Specified Temperature Range Single Supply Dual Supplies Single Supply Dual Supplies Single Supply Dual Supply Symbol VD VA+ VAVREF TA Min 3.135 4.75 2.375 -0.25 -2.625 -40 Typ 3.3 5 2.5 0 -2.5 2.5 2.5 Max 5.25 5.25 2.625 0.25 -2.375 +85 Unit V V V V V V V C
ANALOG CHARACTERISTICS
Parameter Dynamic Performance Dynamic Range (OUT) Dynamic Range (BUF) Total Harmonic Distortion (OUT) Total Harmonic Distortion (BUF) Input Characteristics Bit Rate (TDATA) Full Scale Bandwidth Wideband Max Amplitude One's Density Input Range (Note 1) (Note 2) fTDATA BWFS AWB IROD 25 MCLK/8 200 -20 75 bits/sec Hz dBFS % Unloaded Unloaded 1 k load Unloaded Unloaded 1 k load SNROUT SNRBUF THDOUT THDBUF 110 100 100 114 106 106 -118 -100 -90 -112 -95 -85 dB dB dB dB dB dB Symbol Min Typ Max Unit
Notes: 1. Max amplitude for operation above 200 Hz is TBSGAIN = 0x0078E5. 2. Specification guaranteed by design. These are the negative and positive full scale limits for the TDATA bitstream.
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ANALOG CHARACTERISTICS (CONTINUED)
Parameter Analog Outputs Differential Output Level Absolute Accuracy Relative Accuracy Offset Error Full Scale Drift Offset Drift Analog Output Load at BUF Voltage Reference Input VREF VREF Current Power Supplies Power Supply Rejection DC Power Supply Currents Normal Power Mode LPWR = 0; MCLK = 2.048 MHz Low Power Mode LPWR = 1; MCLK = 1.024 MHz (Note 6) (Note 7 and 8) Analog Digital Analog Digital VA VD VA VD 7.8 100 5.0 100 mA A mA A A A A A PSRR 90 dB (Note 4, 5) VREFV VREFI 2.5 120 V A (Note 3) (Note 3) Load Resistance Load Capacitance VDIF ABS REL VOS FSD VOD RL CL 1 5 VP-P %FS %FS %FS ppm/C V/C k pF Symbol Min Typ Max Unit
1 0.2
5 1 -
2 1.8
1 100
Power Down Mode
Analog Digital Analog Digital
VA VD VA VD
-
400 100 2 2
-
Sleep Mode
3. Specification is for the parameter over the specified temperature range and is for the CS4373 only and does not include the effects of external components. 4. A 2.5 V voltage reference results in the highest dynamic range and best signal-to-noise performance, though smaller reference voltages may be used. 5. VREF is defined as {(VREF+) - (VREF-)} and Inputs must satisfy: VA- < VREF- < VREF+ < VA+ 6. Power Supply Rejection is tested by applying a 100 mVP-P 50 Hz signal to each supply. 7. All outputs unloaded. All digital inputs forced to VD or GND respectively. VA+ = 5 V; VA- = 0; VD+ = 3.3 V. 8. In Low Power Mode LPWR = 1, the Master Clock MCLK is reduced to 1.024 MHz. This reduces the signal bandwidth by a factor of 2.
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DIGITAL CHARACTERISTICS
Parameter High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Symbol VIH VIL Iin Min 0.6 * VD 0.0 Typ 1 Max VD 0.8 10 Unit V V A
ABSOLUTE MAXIMUM RATINGS
CAUTION: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter DC Power Supplies (Note 9, 10) Positive Digital Positive Analog Negative Analog (Note 11, 12) (Note 12) (Note 13) All Analog Pins All Digital Pins Symbol VD VA+ VAIIN IIN IOUT PDS VINA VIND TA Tstg Min -0.3 -0.3 -3.3 (VA-) - 0.5 -0.5 -40 -65 Max +6.8 +6.8 +0.3 10 50 25 500 (VA+) + 0.5 (VD) + 0.5 85 150 Unit V V V mA mA mA mW V V C C
Input Current, Any Pin Except Supplies Input Current, Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
9. VA+ and VA- must satisfy {(VA+) - (VA-)} < +6.8 V. 10. VD and VA- must satisfy {(VD) - (VA-)} < +7.6 V. 11. Includes continuous over-voltage conditions at the analog input (AIN) pins. 12. Transient current of up to 100 mA can be safely tolerated without SCR latch-up. 13. Total power dissipation, including all input and output currents.
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SWITCHING CHARACTERISTICS
Parameter MCLK Frequency (Note 14) MCLK Duty Cycle MCLK Jitter (In-band or aliased in-band) MCLK Jitter (Out-of-band) Rise Times: Fall Times: Any Digital Input Any Digital Input (Note 15) Normal Power Mode Low Power Mode Symbol fc DCCLK CKJIB CKJOB trise tfall tmss tmsh Min 40 20 20 Typ 2.048 1.024 Max 60 300 1 50 50 Unit MHz MHz % ps ns ns ns ns ns
SYNC Setup Time to MCLK falling SYNC Hold Time after MCLK falling
Notes: 14. If MCLK is removed, the CS4373 enters a sleep mode state. 15. SYNC latched on MCLK falling edge, data output on next MCLK rising edge.
t rise
t fall 0.9*VD 0.1*VD
Figure 1. Rise and Fall Times
MCLK
(2.048 MHz)
MSYNC
t0
TDATA
(256 kHz) tmss tmsync ttdat tmclk tmsh
Figure 2. Timing
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INAINA+ OUTR+ OUTF+ INR1+ 0.02F OUTFOUTR+ COG 0.02F COG INF1+ MCLK MSYNC MDATA1 INF1MFLAG1 INR1MFLAG1 MCLK MSYNC MDATA1
Differential Sensor
INBINB+ LPWR GAIN0 GAIN1 GAIN2
CS3301/ CS3302
CS5372
INAINA+ OUTR+ OUTF+ INR2+ INF2+ 0.02F OUTFOUTR+ COG 0.02F COG INF2INR2LPWR MDATA2 MFLAG2 MDATA2 MFLAG2
Differential Sensor
INBINB+ LPWR GAIN0 GAIN1 GAIN2
CS3301/ CS3302
CS5376A
INAINA+ OUTR+ OUTF+ INR1+ 0.02F OUTFOUTR+ COG 0.02F COG INF1+ MCLK MSYNC MDATA1 INF1MFLAG1 INR1MFLAG3 MDATA3
Differential Sensor
INBINB+ LPWR GAIN0 GAIN1 GAIN2
CS3301/ CS3302
CS5372
INAINA+ OUTR+ OUTF+ INR2+ INF2+ 0.02F OUTFOUTR+ COG 0.02F COG INF2INR2LPWR MDATA2 MFLAG2 MDATA4 MFLAG4 GPIO GPIO GPIO GPIO GPIO GPIO GPIO TBSDATA VD 0.01F VA10nF COG CAP+ CAPVD MCLK SYNC TDATA LPWR 0.01F
Differential Sensor
INBINB+ LPWR GAIN0 GAIN1 GAIN2
CS3301/ CS3302
VA+
Switch Control
BUF+ BUF-
CS4373
OUT+ OUTVA+ 10 VREF+ VREF100F VAVA0.01F 0.01F VAMODE0 MODE1 MODE2 ATT0 ATT1 ATT2 DGND
VREF
Figure 4. CS4373 System Connections
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2. TERMINOLOGY
* Dynamic Range (Signal-to-Noise Ratio) - Ratio of the rms magnitude of the theoretical full scale signal to the integrated rms noise from DC to 400 Hz. The following formula is used to calculate this value: SNR = 20log *
Total Harmonic Distortion - Ratio of the power of the fundamental frequency to the sum of the powers of all harmonic frequencies from DC to 400 Hz. The following formula is used to calculate this value: THD = 10log
* * * *
Full Scale Bandwidth - The bandwidth in which the converter can generate a full scale signal while maintaining all performance specifications. Wideband Max Amplitude - The maximum amplitude of the output signal beyond the full scale band-width. Differential Output Level - The peak-to-peak voltage between the analog output pins of the converter. Absolute Accuracy - Variation in the measured output voltage from the theoretical output voltage at each of the attenuation ranges. The following formula is used to calculate this value: absolute accuracy = *100%
*
Relative Accuracy - Variation in the measured output voltage from the theoretical output voltage (relative to measured full scale signal with no attenuation) at each of the attenuation ranges. The following formula is used to calculate this value:
measured attenuated voltage - theoretical attenuated voltage relative accuracy = theoretical attenuated voltage (relative to the measured full scale voltage) *100% *
Offset Error - Variation from the theoretical common mode voltage generated by the converter. The following formula is used to calculate this value: offset error = *100%
* *
Full Scale Drift - The variation of the measured full scale voltage across the specified temperature range. Offset Drift - The variation in the measured offset voltage across the specified temperature range.
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(
measured offset ( theoretical full scale voltage
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(
(
|
(
( measured attenuated voltage - theoretical attenuated voltage theoretical attenuated voltage
(
of the harmonic frequencies ( sum of the powers fundamental frequency power of the
(
9
full scale signal ( rms magnitude of of noise floor rms magnitude
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CS4373
3. GENERAL DESCRIPTION
The CS4373 DAC is designed to fully verify the performance of the acquisition channel. Also, the input switching arrangements allows for verification of sensor source impedance and, in the case a moving-coil geophone, basic parameters of the electro-mechanical transfer function. Test signals are typically generated by the CS5376A or CS5378 digital filter. The CS5376A/78 supplies TDATA with a bitstream at a rate of MCLK/8. The DAC reconstructs the digital bitstream to analog. The full scale output voltage of the DAC matches the maximum input signal rating of the CS3301 and the CS3302 amplifier. A passive, programmable attenuator provides output levels that matches all gain settings of CS3301 and CS3302 while preserving the S/N of the DAC. The DAC can be operated at full scale for signal frequencies up to 200 Hz. For frequencies above 200 Hz the amplitude must be reduced to -20 dB with respect to full scale. and CS3302 for multiple test modes (See Figure 4 on page 8 for typical connection). These outputs can be attenuated to match the gain ranges of the CS3301/3302 using ATT0, ATT1, and ATT2. 4.3 BUF+ / BUFBUF are buffered differential outputs used to test external sensors such as hydrophones or geophones. These outputs are also attenuated internally with the ATT0, ATT1 and ATT2 pins to match the gain ranges of the CS3301 and CS3302 (See Figure 4 on page 8 for typical connection).
5. DIGITAL FILTER INTERFACE
The CS4373 is designed to operate with the CS5376A or CS5378 digital filter. The CS5376A/78 generates the master clock (MCLK), the test bitstream (TDATA) and the synchronization signal input (SYNC). Each of these can be configured within the digital filter to fit the application requirements. 5.1 Signal Bitstream Input - TDATA TDATA is the test bitstream input for the CS4373. It is a one's density bitstream input at a rate of MCLK/8. The digital filter has a bitstream available on its TBSDATA pin. When used with the CS5376A/78, TDATA can be connected directly to TBSDATA for it's bitstream generation. 5.2 Master Clock - MCLK For proper operation, the CS4373 must be provided with a CMOS compatible clock on the MCLK pin. MCLK must have less than 300 ps of in-band jitter to maintain full performance specifications. When used with the CS5376A/78 digital filters, MCLK is automatically generated and is typically 2.048 MHz or 1.024 MHz.
4. ANALOG OUTPUTS
4.1 CAP+ / CAPThe CS4373 DAC needs an anti-alias filter to function properly. The filter is constructed with resistors internal to the CS4373 and a capacitor connected the CAP+ and CAP- pins. This filter will eliminate out of band signals from the OUT and BUF outputs. A 10 nF COG capacitor is required across CAP; other types of capacitors, such as X7R, do not have the stability required. Using the 10 nF COG sets the -3 dB corner of the output anti-alias filter to 40 kHz. 4.2 OUT+ / OUTThe OUT pins are high precision, high output impedance differential outputs designed to test external electronics within the chip set. These outputs directly interface to the CS3301
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5.3 Clock Sync Input - SYNC To synchronize the timing of the digital input bitstream, the CS4373 uses a SYNC signal. When using the CS5376A/78 digital filters, SYNC is automatically generated from a SYNC signal input from the external system. The CS4373 SYNC input is rising edge triggered and resets the internal MCLK counterdivider. defined relative to the VA- supply (see Figure 5). The selected voltage reference should produce less than 1 Vrms of noise in the measurement bandwidth on the VREF+ pin. The digital filter output word rate selection determines the bandwidth over which voltage reference noise affects the CS4373 dynamic range. 6.2 Voltage Reference Configurations For a 2.5 V reference, the Linear Technology LT1019-2.5 voltage reference yields low enough noise if the output is filtered with a low pass RC filter as shown in Figure 5. 6.3 VREF Input Impedance The switched-capacitor input architecture of the VREF+ pin causes the input current required from the voltage reference to change any time MCLK is changed. The input impedance of the voltage reference input is calculated similar to the analog signal input impedance as [1 / (f * C)] where f is the master clock frequency, MCLK, and C is the internal sampling capacitor. A 2.048 MHz MCLK yields a voltage reference input impedance of approximately [1 / (2.048 MHz)*(20 pF)], or about 24 k.
6. VOLTAGE REFERENCE
6.1 Voltage Reference Inputs The CS4373 is designed to operate with a 2.5 V voltage reference applied across the VREF+ and VREF- pins. In a single supply power configuration the VREF+ pin should be connected to the voltage reference output, and the VREF- pin connected to ground. In a dual supply power configuration the voltage reference should be powered from the VA+ and VA- supplies, with the VREF+ pin connected to the voltage reference output and the VREF- pin connected to VA-. Because most 2.5 V voltage references require a power supply voltage greater than 3 V to operate, when powering the voltage reference from dual 2.5 V supplies the reference voltage into the VREF+ pin should be
VA+
0.1 F
10
LT1019-2.5
2.5V REF 0.1 F + 100 F
To VREF+
VA-
0.1 F
To VREF -
Figure 5. 2.5 Voltage Reference Circuit
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6.4 Gain Accuracy Gain accuracy of the CS4373 is affected by variations of the voltage reference input. A change in the voltage reference input impedance due to a change in MCLK could affect gain accuracy when using the higher source impedance configuration of Figure 5. The VREF+ pin input impedance and the external low-pass filter resistor create a voltage divider for the output reference voltage, reducing the effective voltage reference input. If gain error is to be minimized, especially when MCLK is to be changed, the voltage reference should be buffered to have a low output impedance to minimize the effect of the resistive voltage divider. 6.5 Gain Drift Gain drift of the CS4373 due to temperature does not include the temperature drift characteristics of the external voltage reference. Gain drift is not affected by the sample rate or by power supply variations.
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7. TEST MODES
The CS4373 has 7 test modes. The MODE0, MODE1, and MODE2 pins define which mode the part will operate. Table 1 lists the test mode options and corresponding MODE pin settings. The following subsections explain the CS4373 Test Mode Options:
MODE2
Test Mode 0 Test Mode 1 Test Mode 2 Test Mode 3 Test Mode 4 Test Mode 5 Test Mode 6 Test Mode 7 0 0 0 0 1 1 1 1
7.1 Test Mode 0: Reserved 7.2 Test Mode 1: Sensor Test Mode This mode is used to test an external sensor such as a hydrophone or geophone. Both the BUF and OUT are active outputs; and impulse response, linearity, and sensor impedance can be measured in the Sensor Test Mode. See Figure 6 for a typical connection diagram..
Reserved Sensor Test Mode (OUT AND BUF) Electronics Test (OUT ONLY) Sensor Test (BUF ONLY) Common Mode High Voltage/High Current Mode Reserved Sleep Mode
MODE1
0 0 1 1 0 0 1 1
MODE0
0 1 0 1 0 1 0 1
Table 1. Test Modes
C AP+
10nF CO G
CS4373
10nF CO G
CAP+ CAP-
CS4373
C AP-
R
BU F+ BU FHydrophone or G eophone
R
BUF+ BUF-
H ydrophone or G eophone
R
R
OUT+ OUT-
O UT+ O UT-
IN A+ IN A-
CS3301/ CS3302
CS3301/
INA+ INA-
CS3302
IN B+ IN B-
INB+ INB-
Figure 6. Test Mode 1
Figure 7. Test Mode 4
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By placing known resistances on both BUF+ and BUF- (each side of the sensor) the voltage at the buffered outputs (BUF+ and BUF-) can be measured through the CS3301 or CS3302 and compared to the voltage on the precision outputs (OUT+ and OUT-). From these measurements the leakage current of the sensor can be determined Linearity can also be measured from the output of OUT. And when connected to the digital filter, a digital impulse bitstream can be fed directly to the CS4373 to test the impulse response of the system. 7.3 Test Mode 2: Electronics Test Mode In this test mode, outputs BUF are high-Z and only OUT is available. BUF become high impedance to protect any external sensors still connected. This mode can be used to test other system electronics on the board. It should be noted that since only OUT can be used in this mode, and OUT are unbuffered outputs, OUT can only be connected to a high impedance load, such as the CS3301 and CS3302 amplifiers. 7.4 Test Mode 3: Sensor Test Mode As opposed to Test Mode 1, in this mode BUF are the only available outputs. This mode offers another option to test external circuitry. While operating in Test Mode 3, OUT are high impedance to ensure no interference. 7.5 Test Mode 4: Common Mode In this mode the system can be tested using a common mode output from both BUF and OUT. Figure 7 shows BUF and OUT connections internal to the CS4373. Again, since the OUT pins are unbuffered, they must only be connected to a high impedance load, such as the CS3301 and CS3302.
R1 High Current/ High Voltage Electronics OUT+ V2 R2 R1 V1 OUT+
7.6 Test Mode 5: High Voltage/High Current Mode This mode allows connection of the OUT pins to high voltage or high current electronics. Figure 8 shows a typical connection diagram for this operational mode. The CS3301 and CS3302 amplifiers can be used in the configuration as the precision buffers. When using the circuit in Figure 8, the gain of the circuit is defined as: AV = V2 V1 =
( 1+
2R1 R2
)
CAP+ 10nF COG CAP-
CS4373
BUF+ BUF+ -
Figure 8. Test Mode 5
7.7 Test Mode 6: Reserved 7.8 Test Mode 7: Sleep Mode In this mode the chip is put into a low power sleep mode (See Section 9, "Power Modes" on page 15 for more).
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8. ATTENUATION SETTINGS
The DAC outputs can be attenuated to match the gain ranges of the CS3301 and CS3302 amplifiers. Using pins ATT0, ATT1 and ATT2, the outputs of the DAC can be set to one of 7 attenuation options. Table 2 shows each attenuation option.
Attenuation Selection
1 1/2 1/4 1/8 1/16 1/32 1/64 Reserved
high impedance state. 9.4 Power Down The CS4373 is automatically placed into power down if MCLK is disabled. It is equipped with loss of clock detection circuitry to force power down if MCLK is removed. In power down the DAC is inactive and the analog outputs are placed in a high impedance state. When used with the CS5376A or CS5378 the CS4373 will be in this state upon power-up since MCLK is disabled by default.
ATT2
0 0 0 0 1 1 1 1
ATT1
0 0 1 1 0 0 1 1
ATT0
0 1 0 1 0 1 0 1
10. POWER SUPPLY
The CS4373 has one positive analog power supply pin, VA+, one negative analog power supply pin, VA-, one digital power supply pin, VD, and one digital ground pin, DGND. The analog and digital circuitry are separated internally to enhance performance, therefore power must be supplied to all three supply pins. The digital ground pin must be connected to system ground. When used with the CS5376A or CS5378 digital filter the maximum voltage differential between the CS4373 digital supply, VD, and the I/O supplies, (VDD1, VDD2, VDDPAD) must be 0.3 V or less. 10.1 Power Supply Bypassing The analog supply pins, VA+, VA-, should be decoupled to system ground with a 0.1 F capacitor; while the digital supply pin, VD, should be decoupled to system ground with a 0.01 F capacitor. Bypass capacitors can be X7R, tantalum, or any other dielectric types. 10.2 SCR Latch-up Considerations The VA- pin is tied to the CS4373 CMOS substrate and should always be connected to the most negative supply voltage to ensure SCR latch-up does not occur. In general, latch-up may occur when any pin voltage (including the analog inputs) is 0.7 V or more below VA-, or 7.6 V or more above VA-.
Table 2. Attenuator Selection
9. POWER MODES
Five power modes are available when using the CS4373. Normal, low power modes are operational modes; power down and sleep mode are non-operational standby modes. 9.1 Normal Power Mode The normal operational mode for the CS4373, LPWR=0 and MCLK=2.048 MHz, provides the best performance with low power consumption. This power mode is recommended when maximum performance is required. 9.2 Low Power Mode The CS4373 has a low-power operational mode, LPWR = 1 and MCLK = 1.024 MHz, that reduces power consumption at the expense of 3 dB SNR. This operational mode is recommended when minimizing power is more important than maximizing SNR. 9.3 Sleep Mode When selecting Test Mode 7, the CS4373 will be put in a sleep mode in which the DAC is inactive. Each analog output is placed into a
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When using dual analog power supplies, it is recommended to connect the VA- power supply pin to system ground (DGND) using a reversed biased Schottky diode. This configuration clamps the VA- voltage a maximum of 0.3 V above ground to ensure SCR latch-up does not occur during power up. If the VA+ power supply ramps before the VA- supply, the VA- voltage could be pulled above ground through the CS4373. If the VA- supply is unintentionally pulled 0.7 V above the DGND pin, SCR latch-up can occur. 10.3 DC-DC Converter Considerations Many low-frequency measurement systems are battery powered and utilize DC-DC converters to efficiently generate power supply voltages. To minimize interference effects, operate the DC-DC converter at a frequency which is rejected by the digital filter, or operate it synchronous to the MCLK rate. A synchronous DC-DC converter whose operating frequency is derived from MCLK will theoretically minimize the potential for "beat frequencies" to appear in the measurement bandwidth. However this requires the source clock to remain jitter-free within the DC-DC converter circuitry. If clock jitter can occur within the DC-DC converter (as in a PLL-based architecture), it's better to use a nonsynchronous DC-DC converter whose switching frequency is rejected by the digital filter. During PCB layout, do not place high-current DC-DC converters near sensitive analog components. Carefully routing a separate DC-DC "star" ground will help isolate noisy switching currents away from the sensitive analog components. 10.4 Power Supply Rejection Power supply rejection of the CS4373 is frequency dependent. The digital filter rejects power supply noise for frequencies above the filter corner frequency at 130 dB or greater. For frequencies between DC and the digital filter corner frequency, power supply rejection is nearly constant at 90 dB.
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11.PIN DESCRIPTION
Positive Capacitor Output Negative Capacitor Output Positive Buffered Output Negative Buffered Output Positive High Precision Output Negative High Precision Output Positive Analog Power Supply Negative Analog Power Supply Negative Voltage Reference Positive Voltage Reference No Connect No Connect No Connect No Connect
CAP+ CAPBUF+ BUFOUT+ OUTVA+ VAVREFVREF+ NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
LPWR MODE0 MODE1 MODE2 ATT0 ATT1 ATT2 TDATA VD DGND MCLK SYNC DNC DNC
Low Power Mode Enable Mode Select Mode Select Mode Select Attenuation Range Select Attenuation Range Select Attenuation Range Select Signal Bitstream Input Positive Digital Power Supply Digital Ground Master Clock Input Clock Sync Input Do Not Connect Do Not Connect
Pin Name CAP+, CAPBUF+, BUFOUT+, OUTVA+, VAVREF-, VREF+ SYNC MCLK DGND VD LPWR TDATA
Pin # I/O 1, 2 3, 4 5, 6 7, 8 9, 10 17 18 19 20 28 24 O Buffered Output from the Test DAC O High precision output from the Test DAC I
Pin Description
O External Capacitor Connection for Test DAC anti-alias filter
Power supply for the analog section. Refer to the Recommended Operating Conditions for appropriate voltages. Voltage reference for the internal sampling circuits. Refer to the Recommended Operating Conditions for appropriate voltages. Clock Sync Input - A low to high transition resets the internal clock phasing of the DAC. Master Clock Input - a CMOS compatible clock input for the DAC internal master clock. Digital Ground - Ground reference for the digital section. Power supply for the digital section. Refer to the Recommended Operating Conditions for appropriate voltages. Low Power Mode Select - When set high the CS4373 enters into a Low Power Mode. (See Section Section 9, "Power Modes" on page 15 for more on Power Modes) Test DAC Signal Bitstream Input.
I
I
I I
I I I
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CS4373
Pin Name Pin # I/O I Pin Description Attenuation Range Select - Selects the internal attenuation range as detailed in Table 3.
ATT2, ATT1, 21, ATT0 22, 23
Attenuation Selection
1 1/2 1/4 1/8 1/16 1/32 1/64 reserved
ATT2
0 0 0 0 1 1 1 1
ATT1
0 0 1 1 0 0 1 1
ATT0
0 1 0 1 0 1 0 1
Table 3. Attenuator Selection
MODE2, MODE1, MODE0 25, 26, 27 I Mode Selection - Determines the operational mode (0 - 7) of the device as detailed in Table 4.
Mode Selection
Test Mode 0 Test Mode 1 Test Mode 2 Test Mode 3 Test Mode 4 Test Mode 5 Reserved Test Mode 7
Mode
Reserved Sensor Test OUT BUF Common Mode High Voltage Reserved Chip Power Down
MODE2
0 0 0 0 1 1 1 1
MODE1
0 0 1 1 0 0 1 1
MODE0
0 1 0 1 0 1 0 1
Table 4. Mode Selection
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12.ORDERING INFORMATION
Model Temperature Package
CS4373-IS
-40 to +85 C
28-pin SSOP
13.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number Peak Reflow Temp 240 C MSL Rating* 2 Max Floor Life 365 Days
CS4373-IS
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
14.REVISION HISTORY
Revision
PP1 F1
Date
MAR 2003 SEP 2005 Initial preliminary release. Final version. MSL data added.
Changes
DS577F1
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CS4373
15.PACKAGE DIMENSIONS 28L SSOP PACKAGE DRAWING
N
D
E11 A2 A1 A
E
L
e
b2 SIDE VIEW
END VIEW
SEATING PLANE
123
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.064 0.009 0.390 0.291 0.197 0.022 0.025 0
INCHES NOM -0.006 0.069 -0.4015 0.307 0.209 0.026 0.0354 4
MAX 0.084 0.010 0.074 0.015 0.413 0.323 0.220 0.030 0.041 8
MIN -0.05 1.62 0.22 9.90 7.40 5.00 0.55 0.63 0
MILLIMETERS NOM -0.15 1.75 -10.20 7.80 5.30 0.65 0.90 4
NOTE MAX 2.13 0.25 1.88 0.38 10.50 8.20 5.60 0.75 1.03 8
2,3 1 1
JEDEC #: MO-150 Controlling Dimension is Millimeters Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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